integer j, k ; // integer variable

integer i[1:32] ; // array of integer variables

/* time and integer are similar in functionality,

time is an unsigned 64- bit used for time variables */

reg [3*14:1] string ;

/* this defines a vector with range

[msb_expr: lsb_expr] */

a = 0.5 ; // same as 5.0e-1 real variable

b = 1.2E12 ;

c = 26.19_60_e-11 ; // the _'s are used for readability

string = " string example " ;

newtime = $time ;

/* a 6 bit vector register: individual bits din[5],... din[0] */

wire                           tri

wand                           triand

or                             trior

tri0                           tri1

supply0                        supply1

trireg

wire net1;

/* wire and tri have same functionality. tri is used 

for multiple drive internal wire */

trireg (medium) capacitor ;

wand net2; //wired and

wor net3; // wired or

triand [4:0] net4; // multiple drive wand

trior net5; // multiple drive wor

tri0 net6;

tri1 net7;

supply0 gnd; // logic 0 supply wire

supply1 vcc; // logic 1 supply wire

reg [15:0] mem16x512 [0:511];

// 16 bit by 512 word memory

// mem16x512[4] addresses word 4

// the order of lsb:msb or msb:lsb is not important

wire vectored [5:0] neta; /* a six bit vectored net */

tri1 vectored [5:0] netb; /* a six bit vectored tri1

`resetall - resets all compiler directives to default values
`define - text macro substitution
`timescale 1ns / 10ps - specifies time unit/precision
`ifdef, `else, `endif - conditional compilation
`include - file inclusion
`signed, `unsigned -operator selection (OVI 2.0 only)
`celldefine, `endcelldefine - library modules
`default_nettype_wire - default net types
`unconnected_drive pul0|pull1, `nounconnected_drive - pull up or downn unconnected ports.
`protect and `endprotect - encryption capability
`protected and `endprotected - encryption capability
`expand_vectornets and `noexpand_ectornets, 
`autoexpand_vectornets - vector expansion options
`remove_gatename, `noremove_gatenames - remove gatenames for more than one instance.
`remove netname, `noremove_netnames - remove netnames for more than one instance.

$display (“Example of using function”);
$monitor($time, “a = %b, clk = %b, add = %h”,a,clk,add); // monitor signals
$setuphold(posedge clk, datain, setup, hold); // setup and hold checks

$display, $write - utility to display information
$fdisplay, $fwrite - write to file
$strobe, $fstrobe - display, write simulation data
$monitor, $fmonitor - monitor, display/write information to file
$time, $realtime - current simulation time
$finish - exit the simulator
$stop - stop the simulator
$setup - setup timing check
$hold, $width - hold, width timing checks
$setuphold - combines setup and hold timing checks
$readmemb, $readmemh - read stimulus patterns into memory
$sreadmemb, $sreadmemh - load data into memory
$getpattern - fast processing of stimulus patterns
$history - print command history
$save, $restart, $incsave - saving, restarting, incremental saving
$shm_open("database.shm"); -- open/create cwaves database in Verilog-XL

$shm_probe(top_level_module,"AS"); - probes all signals (AS) in the 

                                   scope top_level_module. (Verilog-XL)

$shm_close(); - will close all open shm databases in Verilog-XL

$scale - scaling timeunits from another module
$showscopes - complete list of named blocks, tasks,modules...
$showvars - show variables at scope.

module dff (q,qb,clk,d,rst);
input clk,d,rst; // input signals
output q,qb; output definition

// inout ofr bidirectionals

//Net type declarations
wire d1, db1;

parameter value assignment
parameter delay1 = 3,
                delay2 = delay1 + 1;  // delay2
                                      //shows parameter dependence.

/* Hierarchy primitive instantiation, port connection in this section is by ordered list */

nand #delay1 n1(cf,d1,cbf),
                      n2(cbf,clk,cf,rst);
nand #delay2 n3(d1,d,db1rst),
                       n4(db1,d1,clk,cbf),
                       n5(q,cbf,qb),
                       n6(qb,db1,q,rst);

/****** for debugging model initial begin

#500 force dff_lab.rst = 1;
#550release dff_lab.rst;

// upward path referencing

end ****/

endmodule

module dff_lab;
reg data,rst;
dff d1 (.qb(outb), .q(out), .clk(clk),.d(data),.rst(rst));
//overriding module parameters
defparam
dff_lab.dff.n1.delay1 = 5;
dff_lab.dff.n2.delay2 = 6;
//full path referencing is used.
//overriding by using #(8,9) delay1 = 8...
dff d2 #(8,9) (outc, outd, clk, outb, rst);
//clock generator
always clk = #10 ~clk;
// stimulus continued...

initial begin: stimuli  //named block stimulus
   clk = 1; data = 1; rst = 0;
   #20 rst = 0;
   #20 rst = 0;
   #600 $finish;
end

initial // hierarchy, downward path referencing
   begin
      #100 force dff.n2.rst = 0;
      #200 release dff.n2.rst;
    end
endmosule

// 3 to 1 multiplexor with 2 select

primitive mux32 (Y, in1, in2, in3, s1, s2);
 input in1, in2, in3, s1, s2;
 output Y;
table
// in1 in2 in3 s1 s2    Y
0   ?    ?    0   0  :  0;
1   ?    ?    0   0  :  1;
?   0    ?    1   0  :  0;
?   1    ?    1   0  :  1;
?   ?    0    ?   1  :  0;
?   ?    1    ?   1  :  1;
0   0    ?    ?   0  :  0;
1   1    ?    ?   0  :  1;
0   ?    0    0   ?  :  0;
1   ?    1    0   ?  :  1;
?   0    0    1   ?  :  0;
?   1    1    1   ?  :  1;

endtable
endprimitive

initial q = 1’b1; // initialisation

table
// clock reset data q, q+
? 1 ? : ? : 1 ;
0 0 0 : ? : 0 ;
1 0 ? : ? : - ;
0 0 1 : ? : 1 ;

endtable
endprimitive

// edge triggered D flip flop with active high
// async reset and set.
 Primitive dff (QN, D, CP, R, S);
output QN;
input D, CP, R, S;
reg QN;

table
//D CP R S : Qtn: Qtn+1
1 (01) 0  0 : ?  : 0 ;
1 (01) 0  x : ?  : 0 ;
?   ?  0  x : 0  : 0 ;
0 (01) 0  0 : ?  : 1 ;  // clocked data
0 (01) x  0 : ?  : 1 ;  // pessimism
?   ?  x  0 : 1  : 1 ;  // pessemism
1 (x1) 0  0 : 0  : 0 ;
0 (x1) 0  0 : 1  : 1 ;
1 (0x) 0  0 : 0  : 0 ;
0 (0x) 0  0 : 1  : 1 ;
?   ?  1  ? : ?  : 1 ;  // async clear
?   ?  0  1 : ?  : 0 ;  // async set
?   n  0  0 : ?  : - ;
*   ?  ?  ? : ?  : - ;
?   ? (?0)? : ?  : - ;
?   ?  ?(?0): ?  : - ;
?   ?  ?  ? : ?  : x ;
endtable
endprimitive

if (a < b) // if expression

{c,d} = a + b;

/ concatenate and add operator

initial
   begin : block
      fork
           //This waits for the first event a
           //or b to occur.
           @a disable block
           @b disable block

           // reset at absolute time 20
           #20 reset = 1;
           // data at absolute time 100
           #100 data = 0;
           // data at absolute time 120
           #120 data = 1;
       join
    end

always @(rst)  // simple if ... else
   if (rst)
         // procedural assignment
         q = 0;
   else // remove the above continuous assign
          deassign q;

always @ (WRITE or READ or STATUS)
   begin
   // if - else - if
       if (!WRITE) begin
           out = oldvalue;
       end
       else if  (!STATUS) begin
           q = newstatus;
          STATUS = hold;
       end
       else if  (!READ) begin
          out = newvalue;
       end
end

module d2x8 (select, out); // priority encode
   input [0:2] select
   output [0:7] out;
   reg [0:7] out;

always @ (select) begin
   out = 0;   //default statement
case (select)
   0: begin   // can have begin and end statements for

     out[0] = 1;  // multiple lines...

      end
   1: out[1] = 1;
   2: out[2] = 1;
   3: out[3] = 1;
   4: out[4] = 1;
   5: out[5] = 1;
   6: out[6] = 1;
   7: out[7] = 1;
endcase
end
endmodule

casex (state)
   // treats both x and z as don’t care
   // during comparison: 3’b01z, 3’b01x, 3’b011
   // ... match case 3’b01x
   3’b01x: fsm = 0;
   3’b0xx: fsm = 1;
   default: begin
   // default matches all other occurences
   fsm = 1;
   next_state = 3’b011;
   end
endcase

casez (state)
   //treats z as don’t care during comparison:
   // 3’b11z, 3’b1zz, ... match 3’b1??: fsm = 0;
   3’b1?? : fsm = 0; // is msb   = 1, matches  3’b1??
   3’b01? : fsm = 1;
   default : $display (“wrong state”);
endcase

forever
// should be used with disable or timing control
   @(posedge clock) {co,sum} = a + b + ci;

for (i=0; i< 7; i=i+1)
   memory[i] = 0; // initialize  to 0

for (i=0; i<= bit-width; i = i+1)
   // multiplier using shift left and add
   if (a[i]) out = out + (b << (i-1));

repeat (bit-width) begin
   if (a[0]) out = b + out;
   b = b << 1; // multiplier using
   a = a << 1 ;// shift left and add
end

while (delay) begin @(posedge clk);
   ldlang = oldldlang;
   delay = delay -1;
end

initial forever @(posedge reset)
   disable MAIN;   // disable named block
                   // tasks and modules can also be disabled.

always begin: MAIN  // defining named blocks
   if (!qfull) begin
      #30 recv(new,newdata); // call task
      if (new) begin
         q[head] = newdata;
         head = head + 1;   // queue
      end
   end
   else
       disable recv;
end   // MAIN

task recv;
   output valid;
   output [9:0] data;
   begin
        valid = inreg;
        if (valid) begin
           ackin = 1;
           data = qin;
           wait(inreg);
           ackin = 0;
        end
   end

task instantiation
always begin : MAIN   // named definition
        if (!qfull) begin
        revc(new,newdata);  // call task
        if (new) begin)
           q[head] = newdata;
           head = head + 1;
        end
        end else
           disable recv;
end //MAIN

module foo2 (cs, in1, in2, ns);
   input [1:0] cs;
   input in1, in2;
   output [1:0] ns;
 
   function [1:0] generate_next_state
   input [1:0] current_state;
   input input, input2;
   reg [1:0] next_state
   // input1 causes 0->1 transition
   // input2 causes 1->2 transition
   // 2->0 illegal and unknown states go to 0
   begin
      case( current_state)
        2’h0: next_state = input1 ? 2’h1 : 2’h0;
        2’h1: next_state = input2 ? 2’h2 : 2’h1;
        2’h2: next_state = 2’h0;
        default: next_state = 2’h0;
      endcase
   generate_next_state = next_state;
end
endfunction

assign ns = generate_next_state(cs,in1,in2);

endmodule

/* since only one net15 declaration exists in a give module, only one such 

declarative continuous assignment per signal is allowed */

wire #10 (strong1, pull0) net15 = enable;

/* delay of 10 for continuous assignment with strengths 

of logic 1 as strong1 and lgic 0 as pull0 */

Assign #10 net15 = enable;
assign (weak1, strong0) {s,c} = a + b;

module dff (q, qb, clk, d, rst);
   output q, qb;
   input d, rst, clk;
   reg q, qb, temp;
   always
       #1 qb = ~q;  // procedural assignment

   always @(rst)
      // procedural assignment with triggers
      if (rst) assign q = temp;
      else deassign q;

always @ (posedge clk)
    temp = d;

endmodule

module adder (a,b,ci,co,sum,clk);
   input a,b,ci,clk;
   output co,sum;
   reg co,sum;

always @(posedge clk) // edge control
   // assign co, sum with previous value of a,b,ci
   {co,sum} = #10 a + b + ci;
endmodule

/* assume a = 10, b = 20, c = 30, d = 40 at the start of block */

always @ (posedge clk)
   begin: block
        a <= #10 b;
        b <= #10 c;
        c <= #10 d;

/* at the end of the block + 10 time units, a = 20, b = 30, c = 40 */

  <gate-declaration> ::= <component>

     <drive_strength> ? <delay> ? <gate_instance>

         <,<gate_instance..>>;

Gates

Allows 
Strengths

and, nand, or, nor, xor, xnor, buf, not

Tristate
Drivers

Allows 
Strengths

bufif0, bufif1, notif0, notif1

MOS Switches

No Strengths

nmos, pmos, cmos, rnmos, rpmos, rcmos

Bidirectional
Switch

No strengths, 
non resistive

tran, tranif0, tranif1

Bidirectional
Switch

No strengths, 
resistive

rtran, rtranif0, rtranif1

Bidirectional
Switch

Allows strengths

pullup, pulldown

cmos i1 (out, datain, ncontrol, pcontrol)
nmos i2 (out, datain, ncontrol)
pmos i3 (out, datain, pcontrol)
pullup (neta) (netb);
pulldown (netc);
nor i4 (out, in1, in2, ...);
and i5 (out, in1, in2, ...);
nand i6 (out, in1, in2, ...);
buf i7 (out1, out2, in);
bufif1 i8 (out, in, control);
tranif1 i9 (inout1, inout2, control);

// Gate level instantiation
nor (highz1, strong0) #(2:3:5) (out, in1, in2);
// instantiates a nor gate with out strength of highz1 (for 1)
// and strong0 for 0 #(2:3:5) is the min:typ:max delay

pullup1 (strong1) net1;
//instantiates a logic high pullup
cmos (out, data, ncontol, pcontrol);
// MOS devices

nand #(6:7:8, 5:6:7, 12:16:19) (out, a, b); 

trireg (large) #(0,1,9) capacitor
//charge strength is large
// decay with tr = 0, tf = 1, tdecay = 9

specify // similar to defparam, used for timing 
   specparam delay1 = 25.0, delay2 = 24.0;
 
//edge sensitive delays – some simulators do not support this
(posedge clock) => (out1 +: in1) = delay1, delay2);

//conditional delays
if (OPCDE = 3’h4) (in1, in2 *> out1) = (delay1, delay2);

// +: implies edge sensitive positive polarity
// -: implies edge sensitive -ve polarity
// *> implies multiple paths

// level sensitive delays
if (clock) (in1, in2 *> out1, out2) = 30
// setuphols
   $setuphols(posedge clock &&& reset, in1 &&& reset,
    3:5:6, 2:3:6);
   (reset *> out1, out2) = (2:3:5,3:4:5);

endspecify

<integer data types, with all bases>

<identifiers>

<subranges and slices on right hand side of assignment>

<continuous assignment>

>>,<<,?:,{}
assign (procedural and declarative), begin, end, case, casex, casez, endcase
default
disable
function, endfunction
if, else, else if
input, output, inout
wire, wand, wor, tri
integer, reg
macromodule, module
parameter
supply0, supply1
task, endtask

<intra assignment timing controls>

<delay specifications>

scalared, vectored
small medium large
specify
time (some tools treat these as integers)
weak1, weak0, highz0, highz1, pull0, pull1
$keyword (some tools use these to set synthesis constraints)
wait (some tools support wait with a bounded condition).

<assignment with variable used as bit select on LHS of assignment>

<global variables>

===, !==
cmos,nmos,rcmos,rnmos,pmos,rpmos
deassign
defparam
event
force
fork,join
forever,while
initial
pullup,pulldown
release
repeat
rtran,tran,tranif0
tranif1
rtranif0,rtranif1
table,endtable,primitive,endprimitive